Ratko Pilipović and Nejc Ilc
University of Ljubljana, Faculty of Computer and Information Science
At the workshop, we will demonstrate how to describe, debug, and implement application-specific accelerators on FPGA using the C/C++ language rather than hardware description languages (e.g., VHDL or Verilog). Through simple examples, you will learn how to write kernels that can be synthesised on FPGA fabric, transfer data between the host and an FPGA board, and employ various optimization techniques to make the design more efficient in terms of speed and resource utilization. Leveraging the capabilities of high-level synthesis (HLS), we will develop an accelerator for Cholesky matrix decomposition, utilizing the C/C++ programming language, along with the OpenCL and XRT libraries for development on AMD-Xilinx FPGAs. While the workshop primarily targets AMD-Xilinx FPGA boards, the principles and insights garnered can readily be applied to FPGAs from various other vendors.
The workshop will be conducted in two parts.
In the first part, we will:
- introduce you to heterogeneous computing;
- cover the basics of FPGA architecture and technology;
- give you an overview of HLS programming paradigms and main phases of the synthesis; get to know the XRT software stack and OpenCL
- try to understand and accelerate vector addition on FPGAs
In the second part, we wiil:
- write a kernel for matrix-vector multiplication and optimize it for acceleration on FPGA
- explore various HLS pragmas to improve the processing of HLS-synthesised kernel
- optimize host code to employ multiple compute units
- implement kernel for Cholesky decomposition
The workshop is intended for researchers, engineers, students, and anyone interested in accelerating algorithm performance using FPGA technology.
- Familiarity with an SSH client and SLURM middleware is required. Refer to the contents of the workshop Supercomputing Essentials
- Knowledge of the C/C++ programming language.
Upon completing the workshop, you will:
- understand the operation of heterogeneous computer systems with FPGA;
- be familiar with FPGA technology;
- grasp the concepts of OpenCL and XRT software frameworks and HLS;
- know how to write, translate, and run programs for FPGA;
- be proficient in using HLS directives for design optimization.
The program code utilized in the course can be accessed from the repository.
To download it to the cluster, use the following command:
git clone https://repo.sling.si/ratkop/programming-fpga.git
The material is published under the Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International license. ↩
The workshop is prepared by SLING - Slovenian National Competence Centre for Supercomputing under the auspices of the European project EuroCC 2, which aims to establish national competence centres for high-performance computing. More information about the EuroCC 2 project can be found on the SLING website. The EuroCC 2 project is funded by the European Union. It is financed by the Joint Undertaking for High-Performance Computing (EuroHPC JU) and by Germany, Bulgaria, Austria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Greece, Hungary, Ireland, Italy, Lithuania, Latvia, Poland, Portugal, Romania, Slovenia, Spain, Sweden, France, Netherlands, Belgium, Luxembourg, Slovakia, Norway, Turkey, North Macedonia, Iceland, Montenegro, and Serbia under grant agreement No 101101903. ↩